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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. 00b 11/28/05 issi ? IS43R16160A copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? clock frequency: 200, 166 mhz ? power supply (v dd and v ddq ) ddr 333: 2.5v + 0.2v ddr 400: 2.6v + 0.1v ? sstl 2 interface ? four internal banks to hide row pre-charge and active operations ? commands and addresses register on positive clock edges (ck) ? bi-directional data strobe signal for data cap- ture ? differential clock inputs (ck and ck ) for two data accesses per clock cycle ? data mask feature for writes supported ? dll aligns data i/o and data strobe transitions with clock inputs ? half-strength and full-strength drive strength options ? programmable burst length for read and write operations ? programmable cas latency (2, 2.5, or 3 clocks) ? programmable burst sequence: sequential or interleaved ? burst concatenation and truncation supported for maximum data throughput ? auto pre-charge option for each read or write burst ? 8192 refresh cycles every 64ms ? auto refresh and self refresh modes ? pre-charge power down and active power down modes ? lead-free available 16meg x 16 256-mbit ddr sdram preliminary information november 2005 device overview issi?s 256-mbit ddr sdram achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. the 268,435,456-bit memory array is internally organized as four banks of 64m-bit to allow concurrent operations. the pipeline allows read and write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. the programmable features of burst length, burst sequence and cas latency enable further advantages. the device is available in 16-bit data word size. input data is regis- tered on the i/o pins on both edges of data strobe signal(s), while output data is referenced to both edges of data strobe and both edges of ck. commands are registered on the positive edges of ck. auto refresh, active power down, and pre-charge power down modes are enabled by using clock enable (cke) and other inputs in an industry-standard sequence. all input and output voltage levels are compatible with sstl 2. key timing parameters parameter -5 -6 unit ddr400 ddr333 clock cycle time cas latency = 3 5 6 ns cas latency = 2.5 6 6 ns cas latency = 2 7.5 7.5 ns clock frequency cas latency = 3 200 166 mhz cas latency = 2.5 166 166 mhz cas latency = 2 133 133 mhz
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A pin configurations 66 pin tsop - type ii for x16 pin descriptions a0-a12 row address input a0-a8 column address input ba0, ba1 bank select address dq0 to dq15 data i/o ck, ck system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v ddq ldqs nc vdd nc ldm we cas ras cs nc ba0 ba1 a10 a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 25 26 27 28 2 9 30 31 32 33 66 65 64 63 62 61 60 5 9 58 57 56 55 54 53 52 51 50 4 9 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq 9 v dd q dq8 nc v ssq udqs nc vref vss udm ck ck cke nc a12 a11 a 9 a8 a7 a6 a5 a4 vss we write enable ldm, udm x16 input mask ldqs, udqs data strobe v dd power vss ground v ddq power supply for i/o pin vss q ground for i/o pin v ref input reference voltage nc no connection
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. 00b 11/28/05 issi ? IS43R16160A pin functions symbol type function (in detail) a0-a12 i nput pin address inputs are sampled during several commands. during an active command, a0-a12 select a row to open. during a read or write command, a0-a8 select a starting column for a burst. during a pre-charge command, a10 determines whether all banks are to be pre-charged, or a single bank. during a load mode register command, the address inputs select an operating mode. ba0, ba1 input pin bank address inputs are used to select a bank during active, pre-charge, read, or write commands. during a load mode register command, ba0 and ba1 are used to select between the base or extended mode register cas input pin cas is column access strobe, which is an input to the device command along with ras and we . see ?command truth table? for details. cke input pin clock enable: cke high activates and cke low de-activates internal clock signals and input/output buffers. when cke goes low, it can allow self refresh, pre-charge power down, and active power down. cke must be high during entire read and write accesses. input buffers except ck, ck , and cke are disabled during power down. cke uses an sstl 2 input, but will detect a lvcmos low level after vdd is applied. ck, ck input pin all address and command inputs are sampled on the rising edge of the clock input ck and the falling edge of the differential clock input ck . output data is referenced from the crossings of ck and ck . cs input pin the chip select input enables the command decoding block of the device. when cs is disabled, a nop occurs. see ?command truth table? for details. multiple ddr sdram devices can be managed with cs . ldm, udm input pin these are the data mask inputs. during a write operation, the data mask input allows masking of the data bus. dm is sampled on each edge of dqs. there are two data mask input pins for the x16 ddr sdram. each input applies to dq0-dq7, or dq8-dq15. ldqs, udqs input/output pin these are the data strobe inputs. the data strobe is used for data capture. during a read operation, the dqs output signal from the device is edge- aligned with valid data on the data bus. during a write operation, the dqs input should be issued to the ddr sdram device when the input values on dq inputs are stable. there are two data strobe pins for the x16 ddr sdram. each of the two data strobe pins applies to dq0-dq7, or dq8-dq15. dq0-dq15 input/output pin the pins dq0 to dq15 represent the data bus. for write operations, the data bus is sampled on data strobe. for read operations, the data bus is sampled on the crossings of ck and ck . nc ? no connect: this pin should be left floating. these pins could be used for 256mbit or higher density ddr sdram. ras input pin ras is row access strobe, which is an input to the device command along with cas and we . see ?command truth table? for details. we input pin we is write enable, which is an input to the device command along with ras and cas . see ?command truth table? for details. vddq power supply pin vddq is the output buffer power supply. vdd power supply pin vdd is the device power supply. vref power supply pin vref is the reference voltage for sstl 2. vssq power supply pin vssq is the output buffer ground. vss power supply pin vss is the device ground.
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A block diagram row decoder memory array bank 0 8192 x 256 x32 bit column decoder sense amplifier & i(o) bus row decoder memory array bank 1 column decoder sense amplifier & i(o) bus row decoder memory array bank 2 column decoder sense amplifier & i(o) bus row decoder memory array bank 3 column decoder sense amplifier & i(o) bus input buffer output buffer dq 0 -dq 15 column address counter column address buffer row address buffer refresh counter a0 - a12, ba0, ba1 a0 - a8, ap, ba0, ba1 control logic & timing generator ck cke cs ras cas we dm row addresses column addresses dll strobe gen. data strobe ck, ck ck dqs 8192 x 256 x 32 bit 8192 x 256 x 32 bit 8192 x 256 x 32 bit 16m x 16 capacitance* t a = 0 to 70 c, v cc = 2.5v 0.2v, v cc = 2.6v 0.1v for ddr400, f = 1 mhz * note: capacitance is sampled and not 100% tested. absolute maximum ratings* operating temperature range ..................0 to 70 c storage temperature range ................-55 to 150 c v dd supply voltage relative to v ss .....-1v to +3.6v v ddq supply voltage relative to v ss ......................................................-1v to +3.6v vref and inputs voltage relative to v ss ......................................................-1v to +3.6v i/o pins voltage relative to v ss ..........................................-0.5v to v ddq +0.5v power dissipation .......................................... 1.6 w data out current (short circuit) ...................... 50 ma *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. input capacitance symbol min max unit ba0, ba1, cke, cs , ras , (cas , a0-a11, we ) c ini 23.0pf input capacitance (ck, ck )c in2 23.0pf data & dqs i/o capacitance c out 45pf input capacitance (dm) c in3 45.0pf
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. 00b 11/28/05 issi ? IS43R16160A functional description power-up sequence the following sequence is required for power up. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power and clock (clk, clk ), apply nop & take cke high. 4. precharge all banks. 5. issue emrs to enable dll.(to issue ?dll enable? command, provide ?low? to a0, ?high? to ba0 and ?low? to all of the rest address pins, a1~a11 and ba1) 6. issue a mode register set command for ?dll reset?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a8 and ?low? to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command to initialize device operation. note1 every ?dll enable? command resets dll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. extended mode register set (emrs) the extended mode register stores the data for enabling or disabling dll. the default value of the extend- ed mode register is not defined, therefore the extended mode register must be written after power up for en- abling or disabling dll. the extended mode register is written by asserting low on cs , ras, cas , we and high on ba 0 (the ddr sdram should be in all bank precharge wi th cke already high prior to writing into the extended mode register). the state of address pins a 0 ~ a 12 and ba 1 in the same cycle as cs , ras , cas and we low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a 0 is used for dll enable or disable. ?high? on ba 0 is used for emrs. all the other address pins except a 0 and ba 0 must be set to low for proper emrs operation. a 1 is used at emrs to indicate i/o strength a 1 = 0 full strength, a 1 = 1 half strength. refer to the table for specific codes. power up sequence & auto refresh(cbr) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc min. 200 cycle ?? ck, ck ?? ?? ?? ?? ?? ?? emrs mrs 2 clock min. 200 s power up to 1st command dll reset 2 clock min. 6 5 47 88 precharge all banks ?? functional description power-up sequence the following sequence is required for power up. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power and clock (clk, clk ), apply nop & take cke high. 4. precharge all banks. 5. issue emrs to enable dll.(to issue ?dll enable? command, provide ?low? to a0, ?high? to ba0 and ?low? to all of the rest address pins, a1~a11 and ba1) 6. issue a mode register set command for ?dll reset?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a8 and ?low? to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command to initialize device operation. note1 every ?dll enable? command resets dll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. extended mode register set (emrs) the extended mode register stores the data for enabling or disabling dll. the default value of the extend- ed mode register is not defined, therefore the extended mode register must be written after power up for en- abling or disabling dll. the extended mode register is written by asserting low on cs , ras, cas , we and high on ba 0 (the ddr sdram should be in all bank precharge wi th cke already high prior to writing into the extended mode register). the state of address pins a 0 ~ a 12 and ba 1 in the same cycle as cs , ras , cas and we low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a 0 is used for dll enable or disable. ?high? on ba 0 is used for emrs. all the other address pins except a 0 and ba 0 must be set to low for proper emrs operation. a 1 is used at emrs to indicate i/o strength a 1 = 0 full strength, a 1 = 1 half strength. refer to the table for specific codes. power up sequence & auto refresh(cbr) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc min. 200 cycle ?? ck, ck ?? ?? ?? ?? ?? ?? emrs mrs 2 clock min. 200 s power up to 1st command dll reset 2 clock min. 6 5 47 88 precharge all banks ??
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and various vendor specific options to make ddr sdram useful for a variety of different applications. the default value of the mode register is not defined, therefore the mode register must be writte n after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba 0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 12 in the same cycle as cs , ras , cas , we and ba0 low is written in the mode register. two clock cycles are required to meet t mrd spec. the mode register contents can be changed using the same com- mand and clock cycle requirements during operation as long as all banks are in the idle state. the mode reg- ister is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency (read latency from column address) uses a 4 ~ a 6 . a 7 is a specific te st mode during production test. a 8 is used for dll reset. a 7 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. 1. mrs can be issued only at all banks precharge state. 2. minimum trp is required to issue mrs command. address bus cas latency a 6 a 5 a 4 latency 0 0 0 reserve 0 0 1 reserve 01 0 2 01 1 3 1 0 0 reserve reserve 10 1 1 1 0 2.5 1 1 1 reserve burst length a 2 a 1 a 0 latency sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve a 7 mode 0 normal 1 test a 3 burst type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. a 8 dll reset 0no 1 yes mode register set 0 rfu : must be set "0" extended mode register mode register dlli/o a 0 dll enable 0 enable 1 disable a 1 i/o strength 0 full 1 half ba 0 a n ~ a 0 0 (existing)mrs cycle 1 extended funtions(emrs) command 2 01 5 34 8 67 ck, ck t ck t mrd precharge all banks mode register set t rp *2 *1 any command ba 1 ba 0 a 3 a 2 a 1 a 0 0t m cas latency bt burst length rfu dll mrs mrs a 12 to 0
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. 00b 11/28/05 issi ? IS43R16160A mode register set timing burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). two parameters define how the burst mode will operate: burst sequence and burst length. these parameters are programmable and are determined by address bits a 0 ?a 3 during the mode register set command. burst type defines the sequence in which the burst data will be delivered or stored to the sdram. two types of burst sequence are supported: sequential and interleave. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to values of 2, 4, or 8. see the burst length and sequence table below for programming information. burst length and sequence burst length starting length (a 2 , a 1 , a 0 ) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 t5 t0 t1 t2 t3 t4 t6 t7 t8 t rp t mrd t ck pre- all mrs/emrs any mode register set (mrs) or extended mode register set (emrs) can be issued only when all banks are in the idle state. ck, ck command i f a mrs command is issued to reset the dll, then an additional 200 clocks must occur prior to issuing any new command t9 t o allow time for the dll to lock onto the clock.
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the ddr sdram has four independent banks, so two bank select addresses (ba 0 and ba 1 ) are supported. the bank activate command must be applied before any read or write operation can be executed. the delay from the bank activate command to the first read or write command must meet or exceed the minimum ras to cas delay time (t rcd min). once a bank has been activated, it must be pre- charged before another bank activate command can be applied to the same bank. the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd min). bank activation timing read operation with the dll enabled, all devices operating at the same frequency within a system are ensured to have the same timing relationship between dq and dqs relative to the ck input regardless of device density, pro- cess variation, or technology generation. the data strobe signal (dqs) is driven off chip simultaneously with the output data (dq) during each read cycle. the same internal clock phase is used to drive both the output data and data strobe signal off chip to minimize skew between data strobe and output data. this internal clock phase is nominally aligned to the input differential clock (ck, ck ) by the on-chip dll. therefore, when the dll is enabled and the clock fre- quency is within the specified range for proper dll operation, the data strobe (dqs), output data (dq), and the system clock (ck) are all nominally aligned. since the data strobe and output data are tightly coupled in the system, the data strobe signal may be de- layed and used to latch the output data into the receiving device. the tolerance for skew between dqs and dq (t dqsq ) is tighter than that possible for ck to dq (t ac ) or dqs to ck (t dqsck ). t0 t1 t2 t3 tn tn+1 tn+2 tn+3 tn+4 tn+5 ( cas latency = 2; burst length = any) t rrd (min) t rp (min) t rc t rcd (min) begin precharge bank a ck, ck b a/address command bank/col read/a bank/row activate/a activate/b pre/a bank/row activate/a bank bank/row t ras (min)
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. 00b 11/28/05 issi ? IS43R16160A output data (dq) and data strobe (dqs) timing relative to the clock (ck) during read cycles the minimum time during which the output data (dq) is valid is critical for the receiving device (i.e., a mem- ory controller device). this also applies to the data strobe during the read cycle since it is tightly coupled to the output data. the minimum data output valid time (t dv ) and minimum data strobe valid time (t dqsv ) are de- rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to dll jitter and power supply noise. ( cas latency = 2.5; burst length = 4 ) t0 t1 t2 t3 t4 nop nop nop d 0 ck, ck command dqs dq d 2 t dqsck (max) t dqsck (min) d 1 t ac (min) t ac (max) d 3 read nop read preamble and postamble operation prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe signal (dqs), must transition from hi-z to a valid logic low. the is referred to as the data strobe ?read pream- ble? (t rpre ). this transition from hi-z to logic low nominally happens one clock cycle prior to the first edge of valid data. once the burst of read data is concluded and given that no subsequent burst read operations are initiated, the data strobe signal (dqs) transitions from a logic low level back to hi-z. this is referred to as the data strobe ?read postamble? (t rpst ). this transition happens nominally one-half clock period after the last edge of valid data. consecutive or ?gapless? burst read operations are possible from the same ddr sdram device with no requirement for a data strobe ?read? preamble or postamble in between the groups of burst data. the data strobe read preamble is required before the ddr device drives the first output data off chip. similarly, the data strobe postamble is initiated when the device stops driving dq data at the termination of read burst cycles.
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A data strobe preamble and postamble timings for ddr read cycles consecutive burst read operation and effects on the data strobe preamble and postamble ( cas latency = 2; burst length = 2) t0 t1 t2 t3 t4 read nop nop nop d 0 d 1 ck, ck c ommand dqs dq t rpre (max) t rpst (min) t rpre (min) t rpst (max) t dqsq (max) t dqsq (min) nop read b nop nop nop nop read a d0 a d1 a nop d2 a d3 a command dqs dq burst read operation (cas latency = 2; burst length = 4) ck, ck nop d0 b d1 b d2 b d3 b nop read b nop nop nop nop read a d0 a d1 a nop d2 a d3 a command dqs dq burst read operation ( cas latency = 2; burst length = 4) ck, ck nop d0 b d1 b d2 b d3 b
integrated silicon solution, inc. ? 1-800-379-4774 11 rev. 00b 11/28/05 issi ? IS43R16160A auto precharge operation the auto precharge operation can be issued by having column address a 10 high when a read or write command is issued. if a 10 is low when a read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. when the auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the read or write cycle once t ras (min) is satisfied. read with auto precharge if a read with auto precharge command is initiated, the ddr sdram will enter the precharge operation n-clock cycles measured from the last data of the burst read cycle where n is equal to the cas latency pro- grammed into the device. once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (t rp ) has been satisfied. read with autoprecharge timing ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 begin autoprecharge ba act r/w ap nop nop nop nop nop nop ck, ck command dqs dq t ras (min) t rp (min) earliest bank a reactivate t9
12 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A read with autoprecharge timing as a function of cas latency t0 t1 t2 t3 t4 t5 t6 t7 t8 nop rd ap nop nop nop nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 (cas latency = 2, 2.5 burst length = 4) d 0 d 1 d 2 d 3
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. 00b 11/28/05 issi ? IS43R16160A precharge timing during read operation for the earliest possible precharge command without interrupting a read burst, the precharge command may be issued on the rising clock edge which is cas latency (cl) clock cycles before the end of the read burst. a new bank activate (ba) command may be issued to the same bank after the ras precharge time (t rp ). a precharge command can not be issued until t ras (min) is satisfied. read with precharge timing as a function of cas latency t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop read nop nop pre a nop ba nop ck, ck command dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 (cas latency = 2, 2.5; burst length = 4)
14 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A burst stop command the burst stop command is valid only during burst read cycles and is initiated by having ras and cas high with cs and we low at the rising edge of the clock. when the burst stop command is issued during a burst read cycle, both the output data (dq) and data strobe (dqs) go to a high impedance state after a delay (l bst ) equal to the cas latency programmed into the device. if the burst stop command is issued during a burst write cycle, the command will be treated as a nop command. read terminated by burst stop command timing ( cas latency = 2, 2.5; burst length = 2) t0 t1 t2 t3 t4 t5 t6 bst nop nop nop nop read d 0 d 1 ck, ck command dqs dq d 0 d 1 dqs dq c as latency = 2 c as latency = 2.5 l bst l bst
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. 00b 11/28/05 issi ? IS43R16160A read interrupted by a precharge a burst read operation can be interrupted by a precharge of the same bank. the precharge command to output disable latency is equivalent to the cas latency. read interrupted by a precharge timing burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. the memory controller is re- quired to provide an input data strobe (dqs) to the ddr sdram to strobe or latch the input data (dq) and data mask (dm) into the device. during write cycles, the data strobe applied to the ddr sdram is required to be nominally centered within the data (dq) and data mask (dm) valid windows. the data strobe must be driven high nominally one clock after the write command has been registered. timing parameters t dqss (min) and t dqss (max) define the allowable window when the data strobe must be driven high. input data for the first burst write cycle must be applied one clock cycle after the write command is registered into the device (wl=1). the input data valid window is nominally centered around the midpoint of the data strobe signal. the data window is defined by dq to dqs setup time (t qdqss ) and dq to dqs hold time (t qdqsh ). all data inputs must be supplied on each rising and falling edge of the data strobe until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. write preamble and postamble operation prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe signal (dqs), must transition from hi-z to a valid logic low. this is referred to as the data strobe ?write preamble?. this transition from hi-z to logic low nominally happens on the falling edge of the clock after the write com- mand has been registered by the device. the preamble is explicitly defined by a setup time (t wpres (min)) and hold time (t wpreh (min)) referenced to the first falling edge of ck after the write command. t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop read nop nop pre a nop ba nop ck, ck command dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 (cas latency = 2, 2.5; burst length = 4)
16 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A burst write timing once the burst of write data is concluded and given that no subsequent burst write operations are initiated, the data strobe signal (dqs) transitions from a logic low level back to hi-z. this is referred to as the data strobe ?write postamble?. this transition happens nominally one-half clock period after the last data of the burst cycle is latched into the device. once the burst of write data is concluded and given that no subsequent burst write operations are initiated, (cas latency = any; burst length = 4) t0 t1 t2 t3 t4 write nop nop nop d 0 d 1 d 2 d 3 ck, ck c ommand d qs(nom) dq(nom) t wpres t dqss t wpst t dh d 0 d 1 d 2 d 3 dqs(min) dq(min) t dqss (min) d 0 d 1 d 2 d 3 d qs(max) dq(max) t wpres (min) t dqss (max) t ds t ds t dh t wpres
integrated silicon solution, inc. ? 1-800-379-4774 17 rev. 00b 11/28/05 issi ? IS43R16160A write interrupted by a precharge a burst write can be interrupted before completion of the burst by a precharge command, with the only restriction being that the interval that separates the commands be at least one clock cycle. write interrupted by a precharge timing write with auto precharge if a 10 is high when a write command is issued, the write with auto precharge function is performed. any new command to the same bank should not be issued until the internal precharge is completed. the internal precharge begins after keeping t wr (min.). write with auto precharge timing ( cas latency = 2; burst length = 8 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 write a nop pre a nop nop nop nop nop nop nop nop ck, ck command dqs t12 dm d 0 d 1 d 2 d 3 dq data is masked by precharge command data is masked by dm input dqs input ignored d 4 d 5 t wr d 6 ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop wap nop nop nop nop nop nop ba ck, ck command dqs dq t ras (min) t rp (min) ba nop t9 t10 t wr (min) begin autoprecharge
18 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A precharge timing during write operation precharge timing for write operations in drams requires enough time to satisfy the write recovery require- ment. this is the time required by a dram sense amp to fully store the voltage level. for ddr sdrams, a timing parameter (t wr ) is used to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the ?write recovery? operation begins on the rising clock edge after the last dqs edge that is used to strobe in the last valid write data. ?write recovery? is complete on the next 2nd rising clock edge that is used to strobe in the precharge command. write with precharge timing ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop write nop nop nop nop pre a nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 t1 0 t wr d 0 d 1 d 2 d 3 dqs dq t wr ba
integrated silicon solution, inc. ? 1-800-379-4774 19 rev. 00b 11/28/05 issi ? IS43R16160A data mask function the ddr sdram has a data mask function that is used in conjunction with the write cycle, but not the read cycle. when the data mask is activated (dm high) during a write operation, the write is blocked (mask to data latency = 0). when issued, the data mask must be referenced to both the rising and falling edges of data strobe. data mask timing burst interruption read interrupted by a read a burst read can be interrupted before completion of the burst by issuing a new read command to any bank. when the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point, the data from the interrupting read command appears on the bus. read commands can be issued on each rising edge of the system clock. it is illegal to interrupt a read with autoprecharge command with a read command. read interrupted by a read command timing (cas latency = any; burst length = 8) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 nop nop nop nop nop nop nop write ck, ck command dqs dq dm t9 t ds t ds t dh t dh ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 read b nop nop nop nop nop nop da0 da1 db0 db1 read a db2 db3 ck, ck command dqs dq t9
20 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A read interrupted by a write to interrupt a burst read with a write command, a burst stop command must be asserted to stop the burst read operation and 3-state the dq bus. additionally, control of the dqs bus must be turned around to allow the memory controller to drive the data strobe signal (dqs) into the ddr sdram for the write cycles. once the burst stop command has been issued, a write command can not be issued until a minimum delay or latency (l bst ) has been satisfied. this latency is measured from the burst stop command and is equivalent to the cas latency programmed into the mode register. in instances where cas latency is measured in half clock cycles, the minimum delay (l bst ) is rounded up to the next full clock cycle (i.e., if cl=2 then l bst =2, if cl=2.5 then l bst =3). it is illegal to interrupt a read with autoprecharge command with a write command. read interrupted by burst stop command followed by a write command timing write interrupted by a write a burst write can be interrupted before completion by a new write command to any bank. when the pre- vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. the data from the first write command continues to be input into the device until the write latency of the interrupting write command is satisfied (wl=1) at this point, the data from the interrupting write com- mand is input into the device. write commands can be issued on each rising edge of the system clock. it is illegal to interrupt a write with autoprecharge command with a write command. write interrupted by a write command timing ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 bst nop write nop nop nop nop d 0 d 1 read d 0 d 1 d 2 d 3 ck, ck c ommand dqs dq t9 l bst ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 write a nop nop write b nop nop nop nop da0 da1 db0 db1 db2 db3 ck, ck c ommand dqs dq dm t9 write latency dm0 dm1 dm0 dm1 dm2 dm3
integrated silicon solution, inc. ? 1-800-379-4774 21 rev. 00b 11/28/05 issi ? IS43R16160A write interrupted by a read a burst write can be interrupted by a read command to any bank. if a burst write operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the read command must be masked off with the data mask (dm) input pin to prevent invalid data from being written into the memory array. any data that is present on the dq pins coincident with or following the read command will be masked off by the read command and will not be written to the array. the memory controller must give up control of both the dq bus and the dqs bus at least one clock cycle before the read data appears on the outputs in order to avoid contention. in order to avoid data contention within the device, a delay is required (t wtr ) from the last valid data input before a read command can be issued to the device. it is illegal to interrupt a write with autoprecharge command with a read command. write interrupted by a read command timing auto refresh the auto refresh command is issued by having cs , ras , and cas held low with cke and we high at the rising edge of the clock. all banks must be precharged and idle for a t rp (min) before the auto refresh com- mand is applied. no control of the address pins is required once this cycle has started because of the internal address counter. when the auto refresh cycle has completed, all banks will be in the idle state. a delay be- tween the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc (min). commands may not be issued to the device once an auto refresh cycle has begun. cs input must remain high during the refresh period or nop commands must be registered on each rising edge of the ck input until the refresh period is satisfied. auto refresh timing ( cas latency = 2; burst length = 8 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 write nop read nop nop nop nop nop nop nop nop ck, ck command dqs t12 dm d 2 d 3 d 4 d 5 d 0 d 2 d 3 d 4 d 5 d 6 d 1 d 7 dq data is masked by read command data is masked by dm input dqs input ignored d 0 d 1 t wtr t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop ck, ck command cke t11 auto ref any high pre all t rfc t rp
22 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock (ck). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during the self refresh operation, all inputs except cke are ignored. the clock is inter- nally disabled during self refresh operation to reduce power consumption. the self refresh is exited by sup- plying stable clock input before returning cke high, asserting deselect or nop command and then asserting cke high for longer than t srex for locking of dll. the auto refresh is required before self refresh entry and after self refresh exit. power down mode the power down mode is entered when cke is low and exited when cke is high. once the power down mode is initiated, all of the receiver circuits except clock, cke and dll circuit are gated off to reduce power consumption. all banks should be in idle state prior to entering the precharge power down mode and cke should be set high at least 1tck+tis prior to row active command. during power down mode, refresh opera- tions cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (t ref ) of the device. command cke stable clock t srex auto refresh nop self refresh ck, ck cke precharge active read nop active power down power down exit active entry power exit down power entry down precharge precharge command ck, ck
integrated silicon solution, inc. ? 1-800-379-4774 23 rev. 00b 11/28/05 issi ? IS43R16160A truth table 2 ? cke (notes: 1-4) note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and actionn is a result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of 200 clock cycles is needed before applying a read command, for the dll to lock. cken-1 cken current state commandn actionn notes ll power-down x maintain power-down self refresh x maintain self refresh lh power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 5 hl all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry h h see truth table 3
24 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A command cken-1 cken cs ras cas we addr a10/ ap ba note h x llll op code 1,2 h x llll 1,2 device deselect hx hxxx x1 no l h h h bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1 , 3 write hxlhllca l v 1 write with autoprecharge h1 , 4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a11 and ba0~ba1 used for mode register setting during extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs comm and can be issued after trp period from prechagre command. 3. if a read with autoprechar ge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last dat a-in to prechage delay(tdpl) which is also called write recovery tim e (twr) is needed to guarantee that the la st data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are igno red and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation ) op code refresh operation mode register set extended mode register set ddr sdram simplified command truth table
integrated silicon solution, inc. ? 1-800-379-4774 25 rev. 00b 11/28/05 issi ? IS43R16160A truth table 3 ? current state bank n - command to bank n (notes: 1-6; notes appear below and on next page) note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. deselect or nop com- mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. current state /cs /ras / cas /we command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select and activate row) l l l h auto refresh 7 l l l l mode register set 7 row active l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) l h l h read (select column and start new read burst) 10 l l h l precharge (truncate read burst, start precharge) 8 l h h l burst terminate 9 write (auto precharge disabled) l h l h read (select column and start read burst) 10, 11 l h l l write (select column and start new write burst) 10 l l h l precharge (truncate write burst, start precharge) 8, 11
26 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A note: (continued) row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. read w/auto-precharge enabled: starts with regist ration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto-precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rfc is met, the ddr sdram will be in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram will be in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle and no bursts are in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action co lumn include reads or writ es with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking.
integrated silicon solution, inc. ? 1-800-379-4774 27 rev. 00b 11/28/05 issi ? IS43R16160A truth table 4 ? current state bank n - command to bank m (notes: 1-6; notes appear below and on next page) note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. current state /cs /ras /cas /we command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 llhlprecharge read (auto-precharge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7 llhlprecharge write (auto- precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 8 l h l l write (select column and start new write burst) 7 llhlprecharge read (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 3a, 7 l h l l write (select column and start write burst) 3a, 7, 9 llhlprecharge write (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 3a, 7 l h l l write (select column and start new write burst) 3a, 7 llhlprecharge
28 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A note: (continued) read with auto precharge enabled: see following text write with auto precharge enabled: see following text 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other bank may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided). 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action co lumn include reads or writ es with auto precharge enabled and reads or writes wi th auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output.
integrated silicon solution, inc. ? 1-800-379-4774 29 rev. 00b 11/28/05 issi ? IS43R16160A simplified state diagram preall = precharge all banks ckel = enter power down mrs = mode register set ckeh = exit power down emrs = extended mode register set act = active refs = enter self refresh write a = write with autoprecharge refsx = exit self refresh read a = read with autoprecharge refa = auto refresh pre = precharge self auto idle mrs emrs row precharge write write write read read power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh active active power down precharge power down on a read a read a write a burst stop preall precharge preall
30 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A dc operating conditions & specifications dc operating conditions recommended operating conditions(voltage referenced to vss=0v, ta=0 to 70c) notes: 1. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of the same. peak- to-peak noise on v ref may not exceed 2% of the dc value 2.v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . parameter symbol min max unit note supply voltage (for device with a nominal v dd of 2.5v) v dd 2.3 2.7 supply voltage (v dd of 2.6v for ddr400 device) v dd 2.5 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o supply voltage for ddr400 device v ddq 2.5 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current (v out = 1.95v) i oh -16.8 ma output low current (v out = 0.35v) i ol 16.8 ma
integrated silicon solution, inc. ? 1-800-379-4774 31 rev. 00b 11/28/05 issi ? IS43R16160A idd max specifications and conditions (0c < ta < 70c, vddq=2.5v+ 0.2v, vdd=2.5 + 0.2v, for ddr400 device vddq=2.6v+ 0.1v, vdd=2.6 + 0.1v) conditions version symbol -5 -6 unit operating current - one bank active-precharge; trc=trcmin;tck= tck (min); dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 120 110 ma operating current - one bank operation; one bank open, bl=4 idd1 160 140 25 45 44 52 50 30 90 80 25 ma precharge power-down standby current; all banks idle; power - down mode; cke = =vih(min);all banks idle; cke > = vih(min); tck= tck (min); address and other control inputs changing once per clock cycle; vin = vref for dq, dqs and dm idd2f ma precharge quiet standby current; cs# > = vih(min); all banks idle; cke > = vih(min); address and other control inputs stable with keeping >= vih(min) or =< vil (max); vin = vref for dq ,dqs and dm idd2q ma active power - down standby current; one bank active; power-down mode; cke=< vil (max); vin = vref for dq,dqs and dm idd3p ma active standby current; cs# >= vih(min); cke>=vih(min); one bank active; active - precharge; trc=trasmax; tck = tck (min); dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n ma operating current - burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl=2 at tck= tck(min); 50% of data changing at every burst; lout = 0 m a idd4r 270 230 ma operating current - burst write; burst length = 2; writes; conti nuous burst; one bank active address and control inputs changing once per clock cycle; cl=2 at tck= tck(min); dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every burst idd4w 250 210 ma auto refresh current; trc = trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz, 12*tck for ddr333b; distributed refresh idd5 210 200 ma self refresh current; cke =< 0.2v; external clock should be on; tck= tck(min); idd6 33ma operating current - four bank operation; four bank interleaving with bl=4 idd7 400 350 ma tck = tck (min); tck = tck (min);
32 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A ac o per ati ng condit i ons & timing speci fi cati on ac ope r a t ing condit i o n s no te: 1. v i h(max ) = 4. 2v . t he ov ershoot v olt age durat i on is < 3ns at v dd. 2. vil(m i n) = -1. 5v . t he under shoot volt age du rat i on is < 3ns at vs s. 3. vi d is t he m agnit ude of t h e dif f erenc e bet ween t he input level on ck and t he input on ck . 4. t he v al ue of v ix is expec t ed t o equal 0. 5*v ddq of t he t r ans mit t ing device and m u st t r ack va riat ions in t he dc level of t he sam e . electri c al characteristi cs and ac timi ng f or pc400/ pc333/ p c 26 6 -absol ute spec - if ic a ti o n s (n o tes : 1-5, 14 -17 ) (0 c < t a < 70 c ; v ddq = +2 .5v 0.2 v, v dd =+ 2.5v 0 . 2 v for d d r 400 d e v i c e v dd q = +2 .6v 0.1 v, v dd =+2 .6v 0 .1v) param e te r / conditi on s y mb ol m i n m a x uni t note i nput high (logic 1) v olt age, d q , d q s and dm s i gnals v i h (ac ) vre f + 0. 31 v 1 i nput low (logic 0) volt age, dq , dq s and d m signals. v i l( ac) v re f - 0. 31 v 2 i nput dif f erent ial v ol t age, ck and ck input s v i d (ac ) 0. 7 v ddq +0. 6 v 3 i nput cross i n g p oi nt v olt age, c k and ck input s v i x (a c) 0 . 5*vd dq -0. 2 0. 5*v ddq +0. 2 v 4 ac characteristi cs - 5 - 6 parameter sym - bol m in m a x m i n max units no t es ac cess window of dq s f r om c k / c k t a c - 0. 65 0. 65 - 0. 7 0. 7 ns ck high-level w i dt h t ch 0. 45 0. 55 0. 4 5 0. 55 t ck 30 ck low-lev e l wi dth t cl 0. 45 5 10 6 12 0. 55 0. 4 5 0. 55 t ck 30 c l o ck cy cl e t i me c l = 3 (3) t c k n s 5 2 cl = 2. 5 t c k ( 2 .5 ) 6 1 0 6 1 2 ns 5 2 cl = 2 t ck (2) 7. 5 10 7. 5 12 ns 52 dq and dm input hold t i me relat i v e t o dqs t dh 0. 40 0. 4 5 ns 26, 31 dq and dm input set up t i me relat i v e t o dqs t ds 0. 40 0. 4 5 ns 26, 31 dq and dm input pulse w i dt h ( f or each i n - put ) t d i p w 1. 75 1. 7 5 ns 31 ac cess window of dq s f r o m ck/ c k t d q sc k - 0 . 6 0 . 6 - 0 . 6 0 .6 n s dq s i n put high pulse widt h t dq s h 0. 35 0. 3 5 t ck dqs i n put l o w puls e widt h t dq sl 0. 35 0. 3 5 t ck dqs - dq s k e w, dqs t o l a s t dq v a li d, per group, per acce ss t dq s q 0. 40 0. 45 ns 25, 26 w r it e com m and t o f i rst dq s lat c hing t r an - si t i on t dq ss 0. 72 1. 25 0. 7 5 1. 25 t ck dq s f a lli n g edge t o c k r i s i n g - set up t i m e t ds s 0 . 2 0 .2 t ck dq s f a lling edge f r om ck rising - hold ti m e t dsh 0 . 2 0 .2 t ck
integrated silicon solution, inc. ? 1-800-379-4774 33 rev. 00b 11/28/05 issi ? IS43R16160A half c l oc k period t hp t ch, t cl t ch, t cl ns 34 dat a -out high-impedanc e window f r om ck /ck t hz -0. 6 5 + 0. 65 - 0 . 7 +0. 7 ns 18 dat a -out low-impedan ce w i ndow f r om ck /ck t lz -0. 6 5 + 0. 65 - 0 . 7 +0. 7 ns 18 addr ess and c ont ro l input hold t i me (f a s t slew rat e ) t ih f 0. 60 0. 7 5 ns 14 addr ess and c ont ro l input set up t i me (f a s t slew rat e ) t is f 0. 60 0. 7 5 ns 14 addr ess and c ont ro l input hold t i me (s low s l ew rat e ) t ih s 0. 70 0. 8 0 n s 1 4 addr ess and c ont ro l input set up t i me (s low s l ew rat e ) t is s 0. 70 0. 8 0 n s 1 4 lo ad mo de re g i s t e r c o mm and c y - cl e t i me t mrd 2 2 t ck dq -dq s hold, d q s t o f i r s t dq t o g o non - v a lid, per acces s t qh t hp - t qhs t hp - t qhs ns 25, 26 dat a hold s k ew f a c t or t qhs 0 . 5 0 0 .5 5 n s ac t i ve t o p r ec h a r g e com m and t ras 40 15 18 70, 000 42 120, 000 ns 35 act i ve t o re ad wit h aut o pr echarge com m and t r a p n s 4 6 ac t i ve t o a c ti ve /a u t o r e f r e s h com m and period t rc 60 70 72 60 ns aut o r e f r es h c o mm and per i o d t r f c n s 5 0 ac t i ve t o r e ad or w r i t e del ay t rcd 15 18 ns pre char g e c o mm and per i o d t rp 15 18 ns dq s read preamble t rpr e 0. 9 1 . 1 0. 9 1 . 1 t ck 42 dq s read post a mble t rps t 0. 4 0 . 6 0. 4 0 . 6 t ck act i ve bank a t o act i v e bank b c o m- mand t rrd 10 12 ns dq s writ e pream ble t w p re 0. 25 0. 2 5 t ck dq s writ e pream ble set up t i me t w p res 0 0 n s 20, 21 dqs writ e pos tamble t w p st 0. 4 0 . 6 0. 4 0 . 6 t ck 19 w r it e recov e ry t i m e t w r 15 15 ns i n t e rnal w r i t e t o re ad com m and d e l a y t wt r 2 1 t ck dat a valid out put window na t qh - t dqs q t qh - t dqs q ns 25 ac characteristi cs - 5 - 6 parameter sym - bol m in m a x m i n max units no t e s
34 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A av erage pe riodi c ref r es h int e rval t ref i 7 . 8 7. 8 us t e rminat i n g volt age delay t o v d d t vt d 0 0 n s ex i t s e lf ref r es h t o non-rea d com- mand t xs nr 75 75 ns ex i t s e lf r e fr esh to r e a d c o mm and t xs rd 200 200 t ck ac characteristi cs - 5 - 6 parameter sym - bol m in m a x m i n max units no t e s
integrated silicon solution, inc. ? 1-800-379-4774 35 rev. 00b 11/28/05 issi ? IS43R16160A slew rate d e rati n g values (n o t es : 14) 0c t a +7 0c; v ddq = +2.5 v 0.2 v, v dd = + 2 .5 v 0.2 v for ddr4 0 0 v ddq = +2.6 v 0.1 v, v dd = + 2 .6 v 0.1 v slew rate d e rati n g values (n o t e: 3 1) 0 c t a + 70 c ; v dd q = + 2 .5 v 0.2 v, v dd = +2 .5v 0 .2v f o r ddr4 0 0 v ddq = +2.6 v 0.1 v, v dd = + 2 .6 v 0.1 v notes : 1. al l v o l t ag es refe renc ed to v ss. 2 . tes t s for ac tim i n g , i d d , an d el ec tric al ac an d d c c har act e ris t i c s ma y b e c o n duc ted at nom i n a l re fere nce / s upp ly vo lta ge l e v e ls , b u t t he r e la ted sp eci f ic at ion s a nd dev ic e o pera t io n a r e g uara n te ed f o r th e fu ll vo ltag e ra nge s pec ifi ed. 3. o u t put s m e a s u r ed w i th e q u i va le nt l oad : address / com m and slew rate t is t ih units notes 0. 500 v / ns 0 0 ps 14 0. 400 v / ns +50 + 50 ps 14 0. 300 v / ns +100 +100 ps 14 0. 200 v / ns +150 +150 ps 14 da ta, dqs, dm slew rate t ds t dh units notes 0. 50 0v / ns 0 0 ps 31 0. 40 0v / ns + 7 5 + 75 ps 31 0. 30 0v / ns +150 +150 ps 31 0. 20 0v / ns +225 +225 ps 31 o utput ( v out ) v tt 50 ref erenc e p oint 30pf w d d d d
36 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A notes: (continued) 4. ac timing and idd tests may use a vil-to-vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck/ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between vil(ac) and vih(ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. vref is expected to equal vddq/2 of the transmit-ting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on vref may not exceed 2 percent of the dc value. thus, from vddq/2, vref is allowed 25mv for dc error and an additional 25mv for ac noise. 7. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref and must track variations in the dc level of vref. 8. vid is the magnitude of the difference between the input level on ck and the input level on ck . 9. the value of vix is expected to equal vddq/2 of the transmitting device and must track variations in the dc level of the same. 10. idd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 2 for -6 with the outputs open. 11. enables on-chip refresh and address counters. 12. idd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. this parameter is sampled. vdd = +2.5v 0.2v, vddq = +2.5v 0.2v, vref = vss, f = 100 mhz, t a = 25c, vout(dc) = vddq/2, vout (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. command/address input slew rate = 0.5v/ns. for -5 and -6 with slew rates 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ns, timing must be derated: t is and t ih has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 15. the ck/ck input reference level (for timing referenced to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck is vref. 16. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke < 0.3 x vddq is recognized as low. 17. the output timing reference level, as measured at the timing reference point indicated in note 3, is vtt. 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 22. min ( t rc or t rfc) for idd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for idd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras.
integrated silicon solution, inc. ? 1-800-379-4774 37 rev. 00b 11/28/05 issi ? IS43R16160A notes: (continued) 23. the refresh period 64ms. this equates to an average refresh rate of 7.8s. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other specifications - t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided below for duty cycles rang- ing between 50/50 and 45/55. 26. referenced to each output group: x16 = ldqs with dq0-dq7; and udqs with dq8-dq15. 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through to the target ac level, vil(ac) or vih(ac). b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, vil(dc) or vih(dc). 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device.. 30. ck and ck input s lew r ate must b e > 1v/ns. 31. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 32. vdd must not vary more than 4% if cke is not active while any bank is active.
38 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A notes: (continued) 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 35. reads and writes with auto precharge are not allowed to be issued until t ras(min) can be satisfied prior to the internal precharge command being issued. 36. first dqs (ldqs or udqs) to transition to last dq (dq0-dq15) to transition valid. initial jedec specifications suggested this to be same as t dqsq. 37. normal output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure a. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no guaranteed, to lie within the inner bounding lines of the v-i curve of figure a. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure b. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure b. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 volt. 38. reduced output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure c. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure c. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure d. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure d. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 v, and at the same voltage. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 v. 39. the voltage levels used are derived from the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. vih overshoot: vih(max) = vddq+ 1.5v for a pulse width < 3 ns and the pulse wi d th can not be great er than 1 /3 o f the cyc le rate. vil undersho ot: vil(mi n) = -1. 5v for a pulse wi d th < 3ns and the p ulse w idth can not be gre ater than 1/3 of the cycle rate. 41. vdd and vddq must track each other. 42. note 42 is not used.
integrated silicon solution, inc. ? 1-800-379-4774 39 rev. 00b 11/28/05 issi ? IS43R16160A notes: (continued) 43. note 43 is not used. 44. during initialization, vddq, vtt, and vref must be equal to or less than vdd + 0.3v. alternatively, vtt may be 1.35v maximum during power up, even if vdd /vddq are 0 volts, provided a minimum of 42 ohms of series re- sistance is used between the vtt supply and the input pin. 45. note 45 is not used. 46. t rap > t rcd. 47. note 47 is not used. 48. random addressing changing 50% of data changing at every transfer. 49. random addressing changing 100% of data changing at every transfer. 50. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 51. idd2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. idd2q is similar to idd2f except idd2q specifies the address and control inputs to remain stable. although idd2f, idd2n, and idd2q are similar, idd2f is ?worst case.? 52. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. m a x i m u m nom inal h ig h nominal low nominal low nominal high minimum minimum maximum 80 70 60 50 40 30 20 10 0 .0 0.5 1.0 1.5 2.0 2.5 0.0 -120 -100 -80 -60 -40 -20 0 0.5 1.0 1.5 2.0 2.5 0
40 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A ibis: i/v characteristics for input and output buffers normal strength driver 1. the nominal pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the o uter bounding lines the of the v-i curve of figure a. 3. the nominal pullup v-i curve for ddr sdram devices will be withi n the inner bounding lines of the v-i curve of below figure b. 4. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the out er bounding lines of the v-i curve of figure b. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the full variation in the ratio of the nominal pullup to pull down current should be unity 10% , for device drain to source v oltages from 0 to vddq/2 minimum typical low typical high maximum 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 iout(ma) vout(v) maximum typical high minumum iout(ma) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.0 0.5 1.0 1.5 2.0 2.5 typical low v ddq vout(v)
integrated silicon solution, inc. ? 1-800-379-4774 41 rev. 00b 11/28/05 issi ? IS43R16160A figure 25. i/v characteristics for input/output buffers:pull up(above) and pull down(below) table 17. pull down and pull up current values temperature (tambient) typical 25c minimum 70c maximum 0c vdd/vddq ddr333/ddr266 ddr400 typical 2.5v 2.6v minimum 2.3v 2.5v maximum 2.7v 2.7v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical low typical high minimum maximum typical low typical high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -41.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2
42 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A half strength driver 1. the nominal pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the o uter bounding lines the of the v-i curve of figure a. 3. the nominal pullup v-i curve for ddr sdram devices will be withi n the inner bounding lines of the v-i curve of below figure b. 4. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the out er bounding lines of the v-i curve of figure b. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the full variation in the ratio of the nominal pullup to pu lldown current should be unity 10% , for device drain to source v oltages from 0 to vddq/2 iout(ma) minimum typical low typical high maximum 0 10 20 30 40 50 60 70 80 90 0.0 1.0 2.0 iout(ma) vout(v) maximum typical high minumum iout(ma) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.5 1.0 1.5 2.0 2.5 typical low v ddq vout(v)
integrated silicon solution, inc. ? 1-800-379-4774 43 rev. 00b 11/28/05 issi ? IS43R16160A figure 26. i/v characteristics for input/output buffers:pull up(above) and pull down(below) table 18. pull down and pull up current values temperature (tambient) typical 25c minimum 70c maximum 0c vdd/vddq ddr333/ddr266 ddr400 typical 2.5v 2.6v minimum 2.3v 2.5v maximum 2.7v 2.7v pulldown current (ma) pullup current (ma) voltage (v) typical low typical high minimum maximum typical low typical high minimum maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
44 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A the above characteristics are specified under bes t, worst and normal process variation/conditions figure 36 - data input (write) timing di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n figure 37 - data output (read) timing 1. tdqsq max occurs when dqs is the earliest among dqs and dq signals to transition. 2. tdqsq min occurs when dqs is the latest among dqs and dq signals to transition. 3. tdqsq nom, shown for reference, occurs when dqs transitions in the center among dq signal transitions. don't care dq dm d qs di n t ds t dh t ds t dh t dsl t dsh t min dqsq t max dqsq dq d qs t min dqsq t max dqsq t nom dqsq burst length = 4 in the case shown t dv d qs, dq
integrated silicon solution, inc. ? 1-800-379-4774 45 rev. 00b 11/28/05 issi ? IS43R16160A figure 38 - initialize and mode register sets cke lvcmos low level dq ba0, ba1 200 cycles of clk** extended mode register set load mode register, reset dll (with a8 = h) load mode register (with a8 = l) t mrd t mrd t mrd t rp t rfc t rfc t is power-up: vdd and clk stable t = 200s ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqs high-z ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0-a9, a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a10 all banks don't care ck /ck t ck t ch t cl vtt (system*) t vtd vref vdd vddq c ommand mrs nop pre emrs ar ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ar t is t ih ba0=h, ba1=l t is t ih t is t ih ba0=l, ba1=l t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code t is t ih code mrs ba0=l, ba1=l code code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pre all banks t is t ih ra ra act ba * = vtt is not applied directly to the device, however tvtd must be greater than or equal to zero to avoid device latch-up. ** = tmrd is required before any command can be applied, and 200 cycles of ck are required before a read command can be applied. the two auto refresh commands may be moved to follow the first mrs, but precede the second precharge all command. ( ) ( ) ( ) ( ) code code
46 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A figure 39 - power-down mode ck /ck c ommand valid* nop addr cke valid valid don't care no column accesses are allowed to be in progress at the time power-down is entered * = if this command is a precharge (or if the device is already in the idle state) then the power-down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power-down mode shown is active power down. dq dm dqs valid t ck t ch t cl t is t is t ih t is t is t ih t ih t is enter power-down mode exit power-down mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop
integrated silicon solution, inc. ? 1-800-379-4774 47 rev. 00b 11/28/05 issi ? IS43R16160A figure 40 - auto refresh mode ck /ck c ommand nop valid valid nop nop pre a0-a8 cke ra ra a9, a11 a10 ba0, ba1 *bank(s) ba don't care * = "don't care", if a10 is high at this point; a10 must be high if more than one bank is active (i.e. must precharge all active banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh nop commands are shown for ease of illustration; other valid commands may be possible at these times dm, dq and dqs signals are all "don't care"/high-z for operations shown ar nop ar nop act nop one bank all banks t ck t ch t cl t is t is t ih t ih t is t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq dm dqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rc t rp t rc
48 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A figure 41 - self refresh mode ck /ck c ommand nop ar addr cke valid don't care dq dm dqs valid nop t ck clock must be stable before exiting self refresh mode t rp* t ch t cl t is t is t ih t is t is t ih t ih t is enter self refresh mode exit self refresh mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) * = device must be in the "all banks idle" state prior to entering self refresh mode ** = txsnr is required before any non-read command can be applied, and txsrd (200 cycles of clk) are required before a read command can be applied. t xsnr/ txsrd**
integrated silicon solution, inc. ? 1-800-379-4774 49 rev. 00b 11/28/05 issi ? IS43R16160A figure 42 - read - without auto precharge ck /ck command nop nop pre read cke col n ra ra a10 ba0, ba1 bank x *bank x don't care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: t ac/tdqsck = max dq dqs nop nop act nop nop nop valid valid valid dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t ih t is t ih t rpre t rpre t rp t t ra cl = 2 t min hz t max hz t min lz t max lz t max lz t min ac t max t min t max ac bank x a0-a7 a8, a9, a11 do n do n dqsck rpst dqsck rpst t min lz start! autoprecharge
50 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A figure 43 - read - with auto precharge ck /ck command nop nop pre read cke col n ra ra a10 ba0, ba1 bank x *bank x don't care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: tac/tdqsck = max dq dqs nop nop act nop nop nop valid valid valid dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t ih t is t ih t rpre t rpre t rp t t ra cl = 2 t min hz t max hz t min lz t max lz t max lz t min ac t max t min t max ac bank x a0-a7 a8, a9, a11 do n do n dqsck rpst dqsck rpst t min lz
integrated silicon solution, inc. ? 1-800-379-4774 51 rev. 00b 11/28/05 issi ? IS43R16160A figure 44 - bank read access ck /ck command nop nop nop nop read act cke ra ra ra ra ra a10 ba0, ba1 bank x bank x nop nop nop pre dis ap one bank all banks t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times note that trcd > trcd min so that the same timing applies if autoprecharge is enabled (in which case tras would be limiting) t rcd t ras t rc *bank x bank x t rp cl = 2 col n act a0-a7 a8, a9, a11 don't care dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: t ac/tdqsck = max dq dqs t rpre t rpre t t t min hz t max hz t min lz t max lz t max lz t min lz t min ac t max t min t max ac do n do n dqsck rpst dqsck rpst
52 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A figure 45 - write - without auto precharge ck /ck command nop nop nop write cke col n ra ra a10 ba0, ba1 bank x *bank x ba don't care di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times nop nop pre nop valid act nop dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t rp t ih t is t ih ra a0-a7 a8, a9, a11 dq dm dqs di n t t dqss t t c ase 1: t dqss = min c ase 2: t dqss = max dq dm dqs di n t t wr t dqss t t t t wpst dqsh dqsl t wpres wpst dqsh dqsl wpre wpres t wpre t dss t dss t dsh t dsh
integrated silicon solution, inc. ? 1-800-379-4774 53 rev. 00b 11/28/05 issi ? IS43R16160A figure 46 - write - with auto precharge ck /ck command nop nop nop write cke col n ra ra a10 ba0, ba1 bank x ba don't care di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n en ap = enable autoprecharge act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times nop nop nop nop valid valid act nop en ap t ck t ch t cl t is t is t ih t is t is t ih t ih t dal ra valid t ih a0-a7 a8, a9, a11 dq dm dqs di n t t dqss t t c ase 1: t dqss = min c ase 2: t dqss = max dq dm dqs di n t t dqss t t t t wpst dqsh dqsl t wpres wpst dqsh dqsl wpre wpres t wpre t dss t dss t dsh t dsh
54 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 11/28/05 issi ? IS43R16160A figure 47 - bank write access ck /ck command nop nop nop write act cke ra a10 ba0, ba1 bank x bank x don't care di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address nop commands are shown for ease of illustration; other valid commands may be possible at these times nop nop nop nop pre dis ap one bank all banks t ck t ch t cl t is t is t ih t is t is t ih t ih t rcd t ras t ih t is t ih ra a0-a7 a8, a9, a11 col n *bank x ra t wr dq dm dqs di n t t dqss t t c ase 1: t dqss = min c ase 2: t dqss = max dq dm dqs di n t t dqss t t t t wpst dqsh dqsl t wpres wpst dqsh dqsl wpre wpres t wpre t dss t dss t dsh t dsh
integrated silicon solution, inc. ? 1-800-379-4774 55 rev. 00b 11/28/05 issi ? IS43R16160A ordering information commercial range: 0c to +70c frequency speed (ns) order part no. package 200 mhz 5 IS43R16160A-5t 66-pin tsop-ii 200 mhz 5 IS43R16160A-5tl 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16160A-6t 66-pin tsop-ii
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 08/09/05 plastic tsop 66-pin package code: t (type ii) plastic tsop (t - type ii) millimeters inches symbol min max min max ref. std. no. leads (n) 66 a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 ? ? ? ? b 0.24 0.40 0.009 0.016 c 0.12 0.21 0.005 0.0083 d 22.02 22.42 0.867 0.8827 e1 10.03 10.29 0.395 0.405 e 11.56 11.96 0.455 0.471 e 0.65 bsc 0.026 bsc l 0.40 0.60 0.016 0.024 l1 ? ? ? ? zd 0.71 ref 0.028 ref 0 8 0 8 d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.

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